Senior SoC Design Engineer - RTL/Verilog

A leading technology company in Cambridge is looking for a creative SoC Design Engineer. The role involves developing RTL from specifications and verifying compute subsystems. Candidates should have experience in RTL design using Verilog/SystemVerilog and knowledge in computer architecture. The company offers a competitive reward package, including an annual bonus, healthcare, and 25 days of annual leave. Hybrid working options are available.